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datasheet as8221 flexray standard transceiver www.austriamicrosystems.com/flexray/as8221 revision 1.7 1 - 42 1 general description this document is subject to change without notice. the as8221 is a high speed automotive bus driver fully conforming to the flexray electrical physical layer specification v2.1 rev b. the as8221 operates as a bi-directional interface between the flexray communication controller and the twisted-pair copper wiring. the as8221 provides an optimized host controller interface consisting of three low-active pins. the enable (en) and standby (stbn) input pins for mode handling by the microcontroller and the error (errn) out pin where system, chip failures or status information are signalled to the microcontroller. signalling logic high on the enable and standby pin the device will enter normal mode in case no fault condition is given and in this mode the device is fully operational meaning flexray communication is possible. additionally, a receive-only mode is implemented, which can be accessed by the microcontroller where only flexray streams can be received in order to avoid unwanted disturbances on the flexray bus while listening to the bus traffic. in the low-power modes (standby and sleep mode) very low power consumption is achieved. in case of undervoltage at one of the supply voltages (v bat , v cc , and v io ) the device will change its mode to a low-power mode (either standby or sleep mode) a nd the device wi ll signal an error accordingly. in case of low voltage is detected on both v bat and v cc the device will enter the power-off mode, where no operation is possible. a safe mechanism from the low-power modes to power-off mode and vice versa is implemented ensuring that no deadlock can happen during the startup phase. ensuring application in safety critical environments a two wire bus- guardian interface is implemented where additional monitoring circuitries on the electronic-control-unit can activate and deactivate the transmitter and additionally on the receive enable output (rxen) in low-power modes the wake conditions and in normal power modes the received flexray streams can be monitored. a thermal sensor circuit with an integral shutdown mechanism prevents damage to the device in extreme temperature conditions. the symmetrical transient control for the high- and low-side driver for both the bus-minus (bm) and bus-plus (bp) line allows an ideal balance of communications over different network topologies, with excellent emc performance. 2 key features ?? compliant with flexray electrical physical layer specification v2.1 rev. b ?? data transfer up to 10 mbps ?? excellent emc performance. high common mode range ensure excellent emi ?? interface for bus guardian or supervision circuits ?? automatic thermal shutdown protection ?? supports 12v and 24v systems with very low sleep current ?? integrated power management system - two inhibit pins for external voltage supply control - local wake-up input - remote wake-up capability via flexray bus in low-power modes ?? supports 2.5v, 3v, 3.3v, 5v microcontrollers, automatic adaptation to digital interface levels ?? protection against damage due to short circuit conditions on the bus (positive and negative battery voltage) ?? operating temperature range -40oc to +125oc ?? lead-free ssop20 package 3 applications the as8221 flexray standard transceiver is best fitting for automotive flexray nodes where bus wake-up and voltage regulator control for voltage supplies is needed. the device addresses all ecus connected to the permanent battery supply (clamp 30). the as8221 can be used as only ecu wake-up component with very low po wer consumptio n in sleep mode.
as8221 datasheet - applications www.austriamicrosystems.com/flexray/as8221 revision 1.7 2 - 42 figure 1. as8221 flexray standard transceiver block diagram communication controller interface bus guardian interface power supply interface transmitter receiver wake-up detector stbn en errn rxd txd txen bge rxen inh1 inh2 vbat vio vcc gnd bp bm as8221 wake host controller interface vio vio vbat vbat internal logic (il) bus failure detector
as8221 datasheet - contents www.austriamicrosystems.com/flexray/as8221 revision 1.7 3 - 42 contents 1 general description ............................................................................................................ ...................................................... 1 2 key features................................................................................................................... .......................................................... 1 3 applications................................................................................................................... ............................................................ 1 4 pin assignments ................................................................................................................ ....................................................... 5 4.1 pin descriptions............................................................................................................... ..................................................................... 5 5 absolute maximum ratings ....................................................................................................... ............................................... 6 6 electrical characteristics..................................................................................................... ...................................................... 7 7 typical operating characteristics .............................................................................................. ............................................. 13 8 detailed description........................................................................................................... ..................................................... 14 8.1 block description.............................................................................................................. .................................................................. 14 8.2 events......................................................................................................................... ........................................................................ 14 8.3 operating modes ................................................................................................................ ................................................................ 14 8.3.1 normal mode ............................................................................................................. ............................................................ 15 8.3.2 receive-only mode ....................................................................................................... ....................................................... 15 8.3.3 standby mode............................................................................................................ ............................................................ 15 8.3.4 go-to-sleep mode ........................................................................................................ ........................................................ 15 8.3.5 sleep mode .............................................................................................................. ............................................................... 15 8.4 non operating mode ............................................................................................................. ............................................................. 15 8.4.1 power-off............................................................................................................... .............................................................. 15 8.5 undervoltage events ............................................................................................................ .............................................................. 16 8.5.1 undervoltage/voltage recovery v bat ............................................................................................................................... ....... 16 8.5.2 undervoltage/voltage recovery v io ............................................................................................................................... .......... 16 8.5.3 undervoltage/voltage recovery v cc ............................................................................................................................... ......... 16 8.6 power on/off events............................................................................................................ .............................................................. 16 8.7 wake-up events................................................................................................................. ................................................................ 16 8.7.1 remote wake-up event .................................................................................................... ........................................................ 16 8.7.2 local wake-up event ..................................................................................................... ........................................................... 17 9 application information ........................................................................................................ ................................................... 18 9.1 fail silent behavior........................................................................................................... .................................................................. 19 9.1.1 rxen / bge timeout ...................................................................................................... ............................................................ 19 9.1.2 state transitions due to undervoltage detection ......................................................................... ............................................. 19 9.1.3 state transitions due to voltage recovery detection ..................................................................... .......................................... 19 9.2 mode transitions ............................................................................................................... ................................................................. 19 9.2.1 operating mode transitions .............................................................................................. ........................................................ 20 9.2.2 errn signalling ......................................................................................................... ............................................................... 22 9.3 loss of ground ................................................................................................................. .................................................................. 22 9.4 error flags.................................................................................................................... ...................................................................... 22 9.4.1 undervoltage ............................................................................................................ ................................................................. 22 9.4.2 bus error (buserr) ...................................................................................................... ........................................................... 22 9.4.3 short circuit between bp and bm (bp_bm)................................................................................. ............................................. 22 9.4.4 over temperature (ot) ................................................................................................... .......................................................... 22 9.4.5 txen_bge timeout (txen_to).............................................................................................. ................................................. 22 9.4.6 error flag (error) ...................................................................................................... ............................................................ 23 9.5 status flags................................................................................................................... ..................................................................... 23 9.5.1 local wake flag (lwake) ................................................................................................. ....................................................... 23
as8221 datasheet - contents www.austriamicrosystems.com/flexray/as8221 revision 1.7 4 - 42 9.5.2 remote wake flag (rwake) ................................................................................................ ................................................... 23 9.5.3 power on flag (pwon) .................................................................................................... ......................................................... 23 9.6 error flags and status flags read-out .......................................................................................... ................................................... 23 9.6.1 error and status flag bit order ......................................................................................... ........................................................ 24 9.7 bus driver..................................................................................................................... ...................................................................... 24 9.7.1 bus states .............................................................................................................. ................................................................... 24 9.8 transceiver timing ............................................................................................................. ................................................................ 25 9.9 transmitter.................................................................................................................... ...................................................................... 26 9.10 receiver ....................................................................................................................... .................................................................... 27 9.10.1 bus activity and idle detection (only in normal and receive-only mode) ................................................. .................... 28 9.10.2 bus data detection (only in normal and receive-only mode).............................................................. ......................... 28 9.10.3 receiver test signal................................................................................................... ............................................................. 29 9.11 test circuits .................................................................................................................. .................................................................... 30 9.12 application circuits ........................................................................................................... ................................................................ 31 10 appendix....................................................................................................................... ........................................................ 32 10.1 flexray functional classes ..................................................................................................... ........................................................ 32 10.2 flexray parameter comparison ................................................................................................... ................................................... 32 11 package drawings and markings.................................................................................................. ........................................ 39 12 ordering information........................................................................................................... .................................................. 41
as8221 datasheet - pin assignments www.austriamicrosystems.com/flexray/as8221 revision 1.7 5 - 42 4 pin assignments figure 2. pin assignments ssop20 package 4.1 pin descriptions table 1. pin descriptions pin name pin number pin type description inh2 1 analog i/o analog output. inhibit 2 output for switching external voltage regulator inh1 2 analog output. inhibit 1 output for switching external voltage regulator en 3 digital input with pull-down digital input. enable input v io 4 supply pad supply voltage. i/o supply voltage txd 5 digital input with pull-down digital input. transmit data input txen 6 digital input with pull-up digital input. transmitter enable input rxd 7 digital output digital output. receive data output bge 8 digital input with pull-down digital input. bus guardian enable input stbn 9 digital input. standby input reserved 10 analog/digital input/output with pull-down to be connected to gnd or to be unconnected not used 11 - rxen 12 digital output digital output. receive data enable output errn 13 digital output. error diagnosis output and wake status output v bat 14 supply pad supply voltage. battery supply voltage wake 15 analog i/o analog input. local wake-up input gnd 16 supply pad ground bm 17 analog i/o analog input/output. bus line minus bp 18 analog input/output. bus line plus v cc 19 supply pad supply voltage not used 20 - inh1 en vio txd txen rxd bge stbn vcc bp bm gnd wake vbat errn rxen inh2 reserved n.u n.u 1 2 3 4 5 6 7 8 9 10 16 20 19 18 17 15 14 13 11 12 as8221
as8221 datasheet - absolute maximum ratings www.austriamicrosystems.com/flexray/as8221 revision 1.7 6 - 42 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units notes battery supply voltage (v bat ) -0.3 +50 v supply voltage (v cc ) -0.3 +7.0 v supply voltage (v io ) -0.3 +7.0 v dc voltage at en, st bn, errn, txd, rxd, txen, bge, rxen -0.3 v io + 0.3 v v io < v cc dc voltage on pin wake, inh1, inh2 -0.3 v bat + 0.3 dc voltage at bp and bm -40 +50 v input current (latchup immunity) -100 100 ma according to jedec 78 electrostatic discharge (v esd ) 4 kv bp, bm, v bat and wake pin according aec-q100-002 (hbm) 2 kv all other pins according to aec-q100-002 (hbm) 3 kv bp and bm according to flexray physical layer emc measurement specification version 3.0 500 v on all pins aec-q100-011 (charge device model) 750 v corner pins aec-q100-011 (charge device model) 100 v aec-q100-003 (machine model) transient voltage on bp, bm -200 +200 v according to iso7637 part3 test pulses a and b; class c; rl=45 ? , cl= 100 pf; (see figure 18 on page 30) . transient voltage on v bat -200 +200 v according to iso7637 part2 test pulses 1, 2, 3a and 3b; class c; rl=45 ? , cl= 100pf; (see figure 18 on page 30) . +6.5 +50 v according to iso7637 part2 test pulse 4; class c; rl=45 ? , cl= 100pf; (see figure 18 on page 30) . +50 according to iso7637 part2 test pulse 5b; class c; rl=45 ? , cl= 100pf; (see figure 18 on page 30) . total power dissipation (all supplies and outputs) 150 mw storage temperature -55 +150 oc junction temperature -40 +150 oc package body temperature 260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices ?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % moisture sensitivity level 3 represents a maximum floor life time of 168h
as8221 datasheet - electrical characteristics www.austriamicrosystems.com/flexray/as8221 revision 1.7 7 - 42 6 electrical characteristics t vj = -40 to +150 oc, v cc = +4.75v to +5.25v, v bat = 5.5v to +50v, v io = +2.2 to v cc , r l = 45 ? , c l = 100 pf, unless otherwise specified. table 3. electrical characteristics symbol parameter conditions min typ max units supply voltage t amb ambient temperature -40 +25 +125 oc v cc -v io difference of supplies -0.1 3.05 v i bat v bat current consumption v bat =12v; low-power modes t vj < 125oc (see footnote 1) 02650a v bat =12v; low-power modes t vj < 150oc 0 100 a non-low-power modes 0 0.15 1 ma i cc v cc current consumption low-power modes v cc = 0v to +5.25v (see footnote 1) -5 8 20 a non-low-power modes: normal, driver enabled; 02945ma non-low-power modes: normal, driver enabled; r bus = ?? 0715ma non-low-power modes: receive-only 02.010ma i io v io current consumption low-power modes v io = 0v to +5.25v -5 1 5 a non-low power modes 0 15 1000 a state transitions t stbn_rxd delay stbn high to rxd high with wake flag set 1950s t stbn_rxen delay stbn high to rxen high with wake flag set 1950s t sleep_inh1 delay stbn high to inh1 high inh1 high = 80% v bat 11150s t standby_inh2 delay stbn high to inh2 high inh2 high = 80% v bat 11150s t sleep go-to-sleep hold time inh1 low = 20% v bat 10 26 70 s transmitter v bus_diff_d0 differential bus voltage low in normal mode (data0) v bpdata0 - v bmdata0 ; 40 ? r l ? 55 ? -2 -1 -0.6 v v bus_diff_d1 differential bus voltage high in normal mode (data1) v bpdata1 - v bmdata1 ; 40 ? r l ?? 55 ? 0.6 1 2 v ? v bus_diff matching between data0 and data1 differential bus voltage in normal mode v bus_diff_d0 - v bus_diff_d1 40 ? r l ? 55 ? -200 0 200 mv v bus_com_d0 common mode bus voltage in case of data0 in non-low-power modes v bpdata0 /2 + v bmdata0 /2 40 ? r l ? 55 ? 0.4 * v cc 0.5 * v cc 0.6 * v cc v v bus_com_d1 common mode bus voltage in case of data1 in non-low-power modes v bpdata1 /2 + v bmdata1 /2 40 ?? r l ? 55 ? 0.4 * v cc 0.5 * v cc 0.6 * v cc v
as8221 datasheet - electrical characteristics www.austriamicrosystems.com/flexray/as8221 revision 1.7 8 - 42 ? v bus_com matching between data0 and data1 common mode voltage v bus _ com_d0 - v bus _ com_d1 40 ? r l ? 55 ? -200 0 200 mv v bus_diff_idle absolute differential bus voltage in bus idle mode load on bm/bm: 40 ? || 100pf 0 30 mv ibp bmshortmax ibm bpshortmax absolute max current when bp is shorted to bm v bp =v bm 35 +100 ma ibp gndshortmax absolute max current when bp is shorted to gnd v bp = 0v 48 +100 ma ibm gndshortmax absolute max current when bm is shorted to gnd v bm = 0v 48 +100 ma ibp -5vshortmax absolute max current when bp is shorted to -5 v v bp = -5v 48 +100 ma ibm -5vshortmax absolute max current when bm is shorted to -5 v v bm = -5v 48 +100 ma ibp 27vshortmax absolute max current when bp is shorted to 27 v v bp = 27v 71 +100 ma ibm 27vshortmax absolute max current when bm is shorted to 27 v v bm = 27v 71 +100 ma ibp 48vshortmax absolute max current when bp is shorted to 48 v v bp = 48v 72 +100 ma ibm 48vshortmax absolute max current when bm is shorted to 48 v v bm = 48v 72 +100 ma t txd_bus01 delay time from txd to bus positive edge t txd_rise = 5ns 22 50 ns t txd_bus10 delay time from txd to bus negative edge t txd_fall = 5ns 22 50 ns t txd_mismatch delay time from txd to bus mismatch t txd_bus10 - t txd_bus01 -4 0 4 ns t bus10 fall time differential bus voltage 80% - 20% of v bus 3.75 12 18.75 ns t bus01 rise time differential bus voltage 20% - 80% of v bus 3.75 12 18.75 ns t txen_bus_idle_active delay time from txen to bus active 14 50 ns t txen_bus_active_idle delay time from txen to bus idle 10 50 ns t txen_mismatch delay time from txen to bus mismatch |t txen_bus_idle_active - t txen_bus_active_idle | 450ns t bge_bus_idle_active delay time from bge to bus active 15 50 ns t bge_bus_active_idle delay time from bge to bus idle 11 50 ns t bus_idle_active differential bus voltage transition time: idle to active 530ns t bus_active_idle differential bus voltage transition time: active to idle 230ns t txen_timeout txen timeout 1.5 4.9 15 ms table 3. electrical characteristics symbol parameter conditions min typ max units
as8221 datasheet - electrical characteristics www.austriamicrosystems.com/flexray/as8221 revision 1.7 9 - 42 receiver r bp , r bm bp, bm input resistance idle mode; r bus = ? 10 25 40 k ? r diff bp, bm differential input resistance idle mode; r bus = ? 20 50 80 k ? v bpidle , v bmidle idle voltage in non-low-power modes on pin bp, bm non-low-power modes; v txen = v io load on bm/bm: 40 ? || 100pf 0.4 * v cc 0.5 * v cc 0.6 * v cc v v bpidle_low, v bmidle_low idle voltage in low-power modes on pin bp, bm low-power modes load on bm/bm: 40 ? || 100pf -0.2 0 +0.2 v i bpidle absolute idle output current on pin bp -40v < v bp < 50v 027.5ma i bmidle absolute idle output current on pin bm -40v < v bm < 50v 027.5ma i bpleak , i bmleak absolute leakage current, when not powered v bp = v bm = 5v, v cc = 0v, v bat = 0v; v io = 0v 07+25a v busactivehigh activity detection differential input voltage high non-low-power modes; v receive_com : -10v < (v bp , v bm ) < 15v 150 225 400 mv v busactivelow activity detection differential input voltage low non-low-power modes; v receive_com : -10v < (v bp , v bm )< 15v -400 -225 -150 mv v data1 data1 detection differential input voltage pre-condition: activity already detected. non-low-power modes; v receive_com : -10v < (v bp , v bm )< 15v 150 225 300 mv v data0 data0 detection differential input voltage pre-condition: activity already detected. non-low-power modes; v receive_com : -10v < (v bp , v bm )< 15v -300 -225 -150 mv v dataerr mismatch between data0 and data1 differential input voltage 2 x ( ?? v data0 ? - ? v data1 ?? ) / ( ? v data0 ? + ? v data1 ? ) (see footnote 2) 10 % v receive_com max. common mode voltage range when receiving non-low-power modes -10 +15 v t bus_rxd10 delay from bus to rxd negative edge c rxd = 15 pf (see footnote 3) 36 80 ns t bus_rxd01 delay from bus to rxd positive edge c rxd = 15 pf (see footnote 3) 36 80 ns t bit bit time c rxd = 15 pf (see footnote 3) 54 ns t rxd_asym delay time from bus to rxd mismatch c rxd =15 pf; |t bus_rxd10 - t bus_rxd01 | (see footnote 3) (see footnote 4) 05ns t rxd_fall fall time rxd voltage 80% - 20% of v rxd ; c rxd =15 pf (see footnote 3) 25ns table 3. electrical characteristics symbol parameter conditions min typ max units
as8221 datasheet - electrical characteristics www.austriamicrosystems.com/flexray/as8221 revision 1.7 10 - 42 t rxd_rise rise time rxd voltage 20% - 80% of vrxd; crxd=15 pf (see footnote 3) 25ns t busidledetection idle detection time v bus : 400mv ? 0v 50 173 200 ns t busactivitydetection activity detection time v bus : 0v ? 400mv 100 173 250 ns t busidlereaction idle reaction time v bus : 400mv ? 0v 50 192 300 ns t busactivityreaction activity reaction time v bus : 0v ? 400mv 100 200 350 ns wake-up detector t bwu_d0 data0 detection time in remote wake-up pattern -10v < (v bp , v bm ) < 15v 124s t bwu_idle idle or data1 detection time in remote wake-up pattern -10v < (v bp , v bm ) < 15v 124s t bwu_detect total remote wake-up detection time -10v < (v bp , v bm ) < 15v 48 73 140 s v bwuth bus wake-up detection threshold -10v < (v bp , v bm ) < 15v -300 -250 -150 mv v lwuth local wake-up detection threshold 22.84 v i lwul low level input current on local wake pin v bat = 12v; v lwake = 2v for t < t lwufilter -20 -10 -5 a i lwuh high level input current on local wake pin v bat = 12v; v lwake = 4v for t < t lwufilter 51120a t lwufilter local wake filter time 1 20 40 s supply voltage monitor v batthh v bat undervoltage recovery threshold 3.5 4 4.5 v v batthl v bat undervoltage detection threshold 2.5 3 3.5 v v ccthh v cc under-voltage recovery threshold 3.5 4 4.5 v v ccthl v cc undervoltage detection threshold 2.5 3 3.5 v v iothh v io undervoltage recovery threshold 1.25 1.6 2.0 v v iothl v io undervoltage detection threshold 0.75 1.1 1.5 v t uv_detect detection time for undervoltage at v bat , v cc , v io 100 300 700 ms t uv_rec detection time for undervoltage recovery at v bat , v cc , v io 0.7 2 5 ms bus error detection i thl absolute bus current for low current detection normal mode, transmitter enabled 5ma i thh absolute bus current for high current detection normal mode, transmitter enabled 40 ma table 3. electrical characteristics symbol parameter conditions min typ max units
as8221 datasheet - electrical characteristics www.austriamicrosystems.com/flexray/as8221 revision 1.7 11 - 42 v short differential voltage on bp and bm for detecting short circuit between bus lines normal mode, transmitter enabled 225 mv t bus_error bus error detection time normal mode, transmitter enabled 20 s over temperature ot th over temperature threshold 150 171 180 oc ot tl over temperature hysteresis 10 13 20 oc power supply interface ? v oinh high level voltage drop on inh1, inh2 i inh = 0.2ma, v bat = 5.5v 0 0.15 0.8 v ? i il ? leakage current sleep mode, v inh = 0v 05a communication controller interface v txdih threshold for detecting txd as on logical high 0.48 * v io 0.7 * v io v v txdil threshold for detecting txd as on logical low 0.3 * v io 0.48 * v io v i txdih txd high level input current 30 52 100 a i txdil txd low level input current -5 0 5 a v txenih threshold for detecting txen as on logical high 0.48 * v io 0.7 * v io v v txenil threshold for detecting txen as on logical low 0.3 * v io 0.48 * v io v i txenih txen high level input current -5 0 5 a i txenil txen low level input current -100 -50 -30 a v rxdoh rxd high level output voltage i rxd = -4ma, v io = 5v 0.8 * v io 0.9 * v io 1.0 * v io v v rxdol rxd low level output voltage i rxd = 4ma, v io = 5v 0 0.1 * v io 0.2 * v io v host interface v stbnih threshold for detecting stbn as on logical high 0.48 * v io 0.7 * v io v v stbnil threshold for detecting stbn as on logical low 0.3 * v io 0.48 * v io v i stbnih stbn high level input current 30 52 100 a i stbnil stbn low level input current -5 0 5 a t stbn_deb_lp stbn de-bouncing time low- power modes 0.1 1 40 s t stbn_deb_nlp stbn de-bouncing time non-low- power modes 0.1 1 2 s v enih threshold for detecting en as on logical high 0.48 * v io 0.7 * v io v v enil threshold for detecting en as on logical low 0.3 * v io 0.48 * v io v i enih en high level input current 30 50 100 a i enil en low level input current -5 0 5 a table 3. electrical characteristics symbol parameter conditions min typ max units
as8221 datasheet - electrical characteristics www.austriamicrosystems.com/flexray/as8221 revision 1.7 12 - 42 1. en, stbn, errn, txd, rxd, txen , bge, rxen, lwake, inh1, inh2: open 2. test condition: (vbp + vbm) / 2 = 2,5v) 5% 3. for test signal (see figure 17) 4. guaranteed at specified bit time t bit t en_deb_lp en de-bouncing time low-power modes 0.1 1 40 s t en_deb_nlp en de-bouncing time non-low- power modes 0.1 1 2 s v errnoh errn high level output voltage i errn = -4ma, v io = 5v 0.8 * v io 0.9 * v io 1.0 * v io v v errnol errn low level output voltage i errn = 4ma, v io = 5v 0 0.1 * v io 0.2 * v io v bus guardian interface v bgeih threshold for detecting bge as on logical high 0.48 * v io 0.7 * v io v v bgeil threshold for detecting bge as on logical low 0.3 * v io 0.48 * v io v i bgeih bge high level input current 30 51 100 a i bgeil bge low level input current -5 0 5 a v rxenoh rxen high level output voltage i rxen = -4ma, v io = 5v 0.8 * v io 0.9 * v io 1.0 * v io v v rxenol rxen low level output voltage i rxen = 4ma, v io = 5v 0 0.1 * v io 0.2 * v io v read out interface t ro_en_errn propagation delay falling edge en to errn 24.5s t ro_en_timeout error-read-out timeout 25 50 100 s table 3. electrical characteristics symbol parameter conditions min typ max units
as8221 datasheet - typical operating characteristics www.austriamicrosystems.com/flexray/as8221 revision 1.7 13 - 42 7 typical operating characteristics figure 3. bus differential voltage figure 4. bus absolute voltage figure 5. bus differential voltage figure 6. bus differential input resistance
as8221 datasheet - detailed description www.austriamicrosystems.com/flexray/as8221 revision 1.7 14 - 42 8 detailed description the as8221 is a flexray transceiver operating as an interface between the communication controller and the wired bus lines. the as8221 is designed to extend the application range for high speed and safety critical time triggered bus systems in an automotive environ ment. the drivers are short circuit protected against the positive and negative supply voltage to increase the robustness and reliability of auto motive systems. ? the as8221 operates at baudrates up to 10 mbps. 8.1 block description the as8221 consists of 9 functional blocks (see figure 1) : 8.2 events transitions in order to change between the operation modes are possible only if events are detected. the device supports three type of events, events on the host controller interface (stbn, en), detection of undervoltage or supply voltage recovery and wake events. mode changes are only performed upon detected events. 8.3 operating modes the as8221 provides the following operating modes: ?? normal: non-low-power mode ?? receive-only: non-low-power mode ?? standby: low-power mode ?? go-to-sleep: low-power mode ?? sleep: low-power mode table 4. functional blocks functional block short description host controller interface (hci) digital interface between the transceiver and the host controller (hc) the host interface comprises the read-out handler, which delivers failure and status information via the errn pin to the host controller. communication controller interface (cci) digital interface between the transceiver and the flexray communication controller (cc) bus guarding interface (bgi) digital interface between the transceiver and the flexray bus guardian (bg) or monitoring circuitry. power supply interface (psi) the power supply interface consists of the voltage monitor (vm) with two analog inhibit outputs switching external voltage supplies. internal logic (il) the digital signals from the functional blocks of the device are fed into the internal logic where the forwarding of flexray messages from analog side to digital interfaces and vice versa is done. the state machine is embedded in the internal logic and the handling of error, wake, and power-on flags is executed herein. bus failure detector (bfd) temperature protection (tp) the bus failure detector is directly connected to the bus pins, in order to detect several external failure conditions which may occur on the bus. the temperature protection turns off the output driver when reaching the specified internal temperature in order to protect the device. transmitter the transmitter provides the differential signalling according the flexray standard on the bus pins. receiver the receiver captures flexray valid signals at the bus pins and provides the received data streams to the internal logic. wake-up detector (wud) the wake-up detector recognizes valid wake-up frames on the bus, recognizes a wake signal on the local w ake pin and signals va lid wake-up events to the internal logic.
as8221 datasheet - detailed description www.austriamicrosystems.com/flexray/as8221 revision 1.7 15 - 42 8.3.1 normal mode in this mode the transceiver is able to send and receive data signals on the bus. txen and bge enables and disables the transmi ssion of data streams. inh1 and inh2 outputs are set high. rxd reflects bus data and bus state. the error-read-out-mechanism is enabled. in n ormal mode, the transmitter state can be selected as shown in the table 5 . in case the over-temperature flag is set the transmitter will be disabled. the bus wires are terminated to v cc /2 via receiver input resistances. ?? if the differential bus voltage is higher than v busactivehigh or lower than v busactivelow for a time longer than t busactivitydetection , then activity is detected on the bus (bus = active), rxen is switched to logical ?low? and rxd is released. ?? if, after the activity detection, the differential bus voltage is higher than v data1 , rxd is high. ?? if, after the activity detection, the differential bus voltage is lover than v data0 , rxd is low. ?? if the absolute differential bus voltage is lower than v busactivehigh and higher than v busactivelow for a time longer than t busidledetection , then idle is detected on the bus (bus = idle), rxen and rxd are switched to logical ?high? 8.3.2 receive-only mode in receive-only mode the transmitter is disabled but the receiver is active. 8.3.3 standby mode in this mode the transceiver is not able to send and receive data signals from the bus, but the wake-up detector is active. the power consumption is significantly reduced with respect to the non-low-power operation modes. rxd and rxen, reflects the negation of the wake-up flag. inh1 is set to high. if wake-up flag is set then inh2 is high, otherwise it is floating. the error-read-out-mechanism is not enabled. the bus wires are terminated to gnd (bus state: idle_lp). 8.3.4 go-to-sleep mode in this mode the transceiver has the same behavior as in standby mode but if this mode is selected for a time longer than t sleep and the wake flag is cleared the device enters into the sleep mode. 8.3.5 sleep mode in sleep mode only the bus wake and local wake detection is en abled. in1 and in h2 are floating. 8.4 non operating mode the as8221 provides the following non operating mode: 8.4.1 power-off in this mode the transceiver is not able to operate. rxd, rxen are set to high and errn is set to low. inh1 and inh2 are floati ng. the bus wires are not connected to gnd (bus state: idle_hz). table 5. transmitter state bge txen txd transmitter state bus state h l h enabled data1 (bp is driven high, bm is driven low) h l l enabled data0 (bp is driven low, bm is driven high) x h x disabled idle (bp and bm are not driven) l x x disabled idle (bp and bm are not driven)
as8221 datasheet - detailed description www.austriamicrosystems.com/flexray/as8221 revision 1.7 16 - 42 8.5 undervoltage events the device monitors the following three voltage supplies: ?? v bat : battery supply voltage ?? v io : supply voltage for i/o digital level adaptation ?? v cc : supply voltage (+5v) 8.5.1 undervoltage/voltage recovery v bat if v bat voltage falls below v batthl for a time longer than t uv_detect then the undervoltage v bat flag is set and it is reset if v bat exceeds the voltage threshold v batthh for a time longer than t uv_rec or in case a wake-up event has been detected. the flag can be set or reset in all the modes. 8.5.2 undervoltage/voltage recovery v io if v io voltage falls below v iothl for a time longer than t uv_detect then the undervoltage v io flag is set and it is reset if v io exceeds the voltage threshold v iothh for a time longer than t uv_rec or in case a wake-up event has been detected. the flag can be set or reset in all the operation modes. the flag is automatically reset at power-off. 8.5.3 undervoltage/voltage recovery v cc if v cc voltage falls below v ccthl for a time longer than t uv_detect then the undervoltage v cc flag is set and it is reset if v cc exceeds the voltage threshold v ccthh for a time longer than t uv_rec or in case a wake-up event has been detected. the flag can be set or reset in all operation modes. the flag is automatically reset at power-off. 8.6 power on/off events ?? starting from power-off mode a power on event occurs in case v bat undervoltage flag is reset. ?? starting from every operation mode a power-off event occurs in case v bat and v cc undervoltage flags are set. 8.7 wake-up events a wake-up event can be detected only in low-power modes. the wake-up flag is set if the remote or local wake flag is set. the w ake-up flag is reset if both the remote and local wake-up flags are reset. the re mote wake-up flag is set if a remote wake-up event occurs. th e local wake-up flag is set if a local wake-up event occurs. the remote and local wake-up flags are reset entering a low-power mode from a non- low-power mode, entering normal mode, whenever an undervoltage event occurs and at power-off. 8.7.1 remote wake-up event a remote wake-up event, only possible in low-power mode, consists in the reception of at least two consecutive wake-up symbols via the bus within t bwu_detect . the wake-up symbol is defined as data0 longer than t bwu_d0 followed by idle or data1 longer than t bwu_idle as in figure 7 unless an undervoltage or wake-up event is present. figure 7. signal for wake-up pattern recognition t bwu_d0 t bwu_idle v bus t bwu_d0 t bwu_idle t bwu_detect
as8221 datasheet - detailed description www.austriamicrosystems.com/flexray/as8221 revision 1.7 17 - 42 8.7.2 local wake-up event in all low-power modes, if the vo ltage on the wake pin falls below v lwuth for longer than t lwfilter , a local wake-up event is detected. at the same time the biasing of the pin is switched to pull-down. if the voltage on the wake pin rises above v lwuth for longer than t lwfilter , a local wake-up event is detected. at the same time the biasing of the pin is switched to pull-up. the pull up and down mechanism is ac tive in low-power and non-low-power modes. figure 8. wake input pin behavior wake rxd / rxen inh t lwfilter t lwfilter pull up pull up pull down vbat vbat vio
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 18 - 42 9 application information system description. note that the state diagram does not include all the transitions described in table 7 . figure 9. state diagram prefix of ? while ? is an event and suffix in brackets checks the flags or in case of en and stbn the input condition. for example: v rec _v bat while (en=0 and stbn=0). after the event v bat supply voltage recovery is detected, the transition is performed if en and stbn are ?low?. uv _v io whi le (u v _v c c ) power off normal receive only go to sleep standby sleep en=0 while (stbn=1) en=1 while (stbn=1) stbn=0 while (en=0) or uv_v cc while stbn=1 while (en=0) or wake while (en=0 and stbn=1) or v rec _v cc while (en=0 and stbn=1) w a k e w h i l e ( e n = 1 a n d s t b n = 1 ) t h e n ( v r e c _ v c c ) o r v r e c _ v c c w h i l e ( e n = 1 a n d s t b n = 1 ) uv_v cc stbn=0 while (en=1) stbn=1 while (en=1) uv_v bat then (r eset _wake) or uv_v io then (r eset _wake) from any state (except power off) en=0 while (stbn=0) or uv_vcc en=1 while (stbn=0) or wake while (en=1 and stbn=0) or v rec _v cc while (en=1 and stbn=0) timer = t sleep wake while (en=1 and stbn=0) or v rec _v bat while (en=1 and stbn=0) or v rec _v io while (en=1 and stbn=0) stbn = 1 while (en=1) or wake while (en=1 and stbn=1) or v rec _v bat while (en=1 and stbn=1) or v rec _v io while (en=1 and stbn=1) w a k e w h i l e ( e n = 0 a n d s t b n = 0 ) o r v r e c _ v b a t w h i l e ( e n = 0 a n d s t b n = 0 ) o r v r e c _ v i o w h i l e ( e n = 0 a n d s t b n = 0 ) o r v r e c _ v i o w h i l e ( u v _ v c c ) stbn=1 while (en=0) or wake while (en=0 and stbn=1) or v rec _v bat while (en=0 and stbn=1) or v rec _v io while (en=0 and stbn=1) input: en = 1 stbn = 1 output: inh1 = 1 inh2 = 1 input: en = 1 stbn = 0 output: inh1 = 1 inh2 = float input: en = 0 stbn = 1 output: inh1 = 1 inh2 = 1 input: en = 0 stbn = 0 output: inh1 = 1 inh2 = float input: en = x stbn = 0 output: inh1 = float inh2 = float uv_v bat while ( uv_v cc ) or uv_vcc while (uv_v bat ) uv_v bat while ( uv_v cc ) v rec _v bat or v rec _v cc wake while (en=0 and stbn=0) or uv_v cc while (en=0 and stbn=0) or v rec _v cc while (en=0 and stbn=0) or while (uv_v cc ) wake while (en=1 and stbn=0) (en=0 or en=1) or (stbn=1 or stbn=0) while (uv_v bat or uv_v io ) or uv_v bat or uv_v io or uv_v cc or v rec _v cc uv_v bat : undervoltage event and/or flag for v bat supply voltage uv_v io : undervoltage event and/or flag for v io supply voltage uv_v cc : undervoltage event and/or flag for v cc supply voltage v rec _v bat : voltage recovery event and/or flag for v bat supply voltage v rec _v io : voltage recovery event and/or flag for v io supply voltage v rec _v cc : voltage recovery event and/or flag for v cc supply voltage wake : wake event and/or flag
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 19 - 42 9.1 fail silent behavior 9.1.1 rxen / bge timeout in case no edges on rxen and bge within t txen_timeout are detected, the transmitter will stop transmitting the signals on rxd to the bus pins. 9.1.2 state transitions due to undervoltage detection ?? in case of v bat or v io undervoltage is detected, sleep mode will be entered regardless the status of en and stbn. ?? in case v cc undervoltage is detected, standby mode will be entered regardless the status of en and stbn. ?? v bat and v io undervoltage detection have higher priority than v cc undervoltage detection. ?? in case undervoltage at v bat and v cc is detected, power-off mode is entered (bus state: idle_hz). 9.1.3 state transitions due to voltage recovery detection ?? if the voltage recovers the device will enter the mode selected by the en and stbn pins, in case no undervoltage is present at the other supply pins. ?? starting from the power-off, the device enters the st ate selected by the host input pins (en, stbn) only if v bat or v cc recovers (v bat ?? v batthh or v cc ?? v ccthh ) while v io is available (undervoltage flag of v io flag not set). if the v io undervoltage flag is set, the standby mode will be entered. in both cases the power-on flag is set. ?? if v bat ? v batthl and v cc ? v ccthl the device will be in power-off state, thus the bus wires are not terminated (bus state: idle_hz). 9.2 mode transitions in case of power-off event, the device enters power-off regardless vio undervoltage flag, wake-up flags and regardless the sele ction at the host input pins. starting from the power-off the device enters standby only in case a power on event occurs. starting from every operating mode th e device enters sleep in case v bat or v io undervoltage flag is set regardless the v cc undervoltage flag, the wake-up flag and the state of the host input pins. starting from every operating mode except sleep the device enters standby in case v cc undervoltage flag is set and v bat and v io undervoltage flags are not set, regardless the wake-up flag indication and the host input pins state. starting from a low-power mode the device enters the operation mode indicated by the host input pins if a wake-up event occurs. in case all the undervoltage flags are reset the operation mode is selected by the wake-up flag and the host pins according to table 6 . where: h = digital level high, l = digital level low, x = do not care!, floating = the analog output is not driven. table 6. pin signalling and operating modes inputs operation mode output stbn en rxd errn rxen inh1 inh2 hh normal l bus = data_0 not [error flag] l bus = active hh h bus = idle or data_1 h bus = idle h l receive-only l bus = data_0 not [error flag] l bus = active hh h bus = idle or data_1 h bus = idle l h go-to-sleep not [wake-up flag] not [wake-up flag] not [wake-up flag] h floating l l standby not [wake-up flag] not [wake-up flag] not [wake-up flag] h floating l x sleep not [wake-up flag] not [wake-up flag] not [wake-up flag] floating floating x x power-off h l h floating floating
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 20 - 42 notes: 1. if go-to-sleep is selected for more than t sleep then the device will enter sleep only if the wake-up flag is not set otherwise it will remain in go-to-sleep. 2. if wake-up flag is set inh2=h otherwise inh2=floating. 3. starting from sleep, if the wake-up flag is set, the device enters standby regardless the host pins state and uv flags. sta rting from sleep, if the wake-up flag is not set, the only operating mode that can be entered through host pins are the non-low-power mode s. 9.2.1 operating mode transitions table 7. transition table transition event under voltage flag wake flag host input remarks start point destination v io v bat v cc stbn en normal receive-only s l l l x h (1) h ? l standby u l l (1) l ? h(2) x ? lh h go-to-sleep s l l l (2) x ? l(1) h ? lh sleep timer enabled sleep u(1) l ? hl l (2) x ? lh h u l (1) l ? h(2) x ? lh h receive- only normal s l l l x h (1) l ? h standby s l l l (2) x ? l(1) h ? ll ull(1) l ? h(2) x ? lh l sleep u(1) l ? hl l (2) x ? lh l u l (1) l ? h l (2) x ? lh l standby normal ull(1) h ? ll h h wl l(2) h ? l(1) l ? hh h receive-only sll l x(1) l ? hl ull(1) h ? ll h l wl l(2) h ? l(1) l ? hh l go-to-sleep s l l l l l (1) l ? h sleep timer enabled s l l l h l (1) l ? h sleep timer disabled ull(1) h ? ll l h sleep timer enabled wl l(2) h ? l(1) l ? hl h sleep timer disabled sleep u(1) l ? hl l (2) x ? ll l u(1) l ? hl h l x x u l (1) l ? h l (2) x ? ll l standby wl l(2) x ? l(1) l ? hl l ull(1) l ? h(2) x ? ll l ull(1) h ? ll l l sll h l(1) l ? hx s l l h l x (1) l ? h
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 21 - 42 note: s = transition forced via en, stbn; u = transition forced via undervoltage or voltage recovery; w = transition forced via wake (1) indicates the action, that initiates the transition (2) indicates the consequence after performed transition (3) in case the wake flag is set, it is not possible to enter sleep mode through a sleep command, requested by the host. (4) in case an undervoltage on v bat and v cc is detected, the device enters the power-off state. go-to-sleep normal s l l l x (1) l ? hh standby s l l l x l (1) h ? l ull(1) l ? h(2) x ? ll h sleep sll l l l h t ? t sleep u(1) l ? hl l (2) x ? ll h u l (1) l ? h l (2) x ? ll h go-to-sleep w l l l (1) l ? hl h sleep timer disabled sleep normal sll l l(1) l ? hh w(2) x ? l(2) x ? l(2) x ? l(1) l ? hh h u l (1) h ? ll l h h u(1) h ? ll l l h h receive-only sll l l(1) l ? hl w(2) x ? l(2) x ? l(2) x ? l(1) l ? hh h u l (1) h ? ll l h l u(1) h ? ll l l h l standby w(2) x ? l(2) x ? l(2) x ? l(1) l ? hl l u l (1) h ? ll l l l u(1) h ? ll l l l l u(1) h ? ll h l x x go-to-sleep w(2) x ? l(2) x ? l(2) x ? l(1) l ? hl h sleep timer disabled u l (1) h ? ll l l h sleep timer disabled u(1) h ? ll l l l h sleep timer disabled sleep sxx x l x(1) l ? h shl x l(1) l ? hx slh l l(1) l ? hx shh l l(1) l ? hx u x (1) l ? hl l x x u(1) l ? hx x l x x ull(1) l ? hl x x table 7. transition table transition event under voltage flag wake flag host input remarks start point destination v io v bat v cc stbn en
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 22 - 42 9.2.2 errn signalling the errn signalling is shown in table 8 . 9.3 loss of ground whenever a loss of ground is detected, the bus lines are switched idle_hz with the precondition that the host pins are open. ei ther error or no error can be indicated on the errn pin. 9.4 error flags 9.4.1 undervoltage ?? uvv bat _det: the v bat undervoltage flag is set if the v bat voltage falls below v batthl for longer than t uv_detect and is reset if the v bat voltage reaches a voltage level higher than v batthh for longer than t uv_detect . ?? uv v io _ det: the v io undervoltage flag is set if the v cc voltage falls below v ccthl for longer than t uv_detect and is reset if the v cc voltage reaches a voltage level for longer than v ccthh after t uv_detect . ?? uv v cc _ det: the v cc undervoltage flag is set if the v io voltage falls below v iothl for longer than t uv_detect and is reset if the v io volt- age reaches a voltage level higher than v iothh for longer than t uv_detect . 9.4.2 bus error (buserr) the bus error flag is set if 2 consecutive rising edges on the txd pin without any rising edge on the rxd pin are detected or i f 2 consecutive falling edges on the txd pin without any falling edge on the rxd pin are detected. this flag is reset if a rising edge on the t xd pin is followed by a rising edge on rxd pin before the next txd rising edge or if a falling edge on the txd pin is followed by a falling edge on r xd pin before the next txd falling edge. this flag can be set or reset only in normal mode when the transmitter is enabled. the flag is reset at power-off. 9.4.3 short circuit between bp and bm (bp_bm) the bp_bm can only be set or reset in normal mode while the driver is active (edge at txen) for a time longer than t bus_error . the flag is set if the absolute value of the differential voltage is lower than v short for a time t bus_error . the flag is reset in power-off mode and if the set condition is not fulfilled. 9.4.4 over temperature (ot) this flag can only be set or reset in the non-low-power modes. the flag is set if the junction temperature exceeds ot th and it is reset if the junction temperature falls below ot tl . 9.4.5 txen_bge timeout (txen_to) this flag can only be set in normal mode if the driver is enabled (txen is low and bge is high) for a time longer than t txen_max . it is reset during transition on txen or bge or if the device exits normal mode. if the flag is set the driver is disabled. table 8. errn signalling supply voltage flag event v io rwake flag lwake flag host command errn stbn en l x x h h not [error flag] lhxhl if rising edge at en, then not [error flag] else l llxhl if rising edge at en, then not [error flag] else h llllxh lll ? hl x h ? l ll ? hl l x h ? l lhl ? hl x l ll ? hh l x l hxxxxl
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 23 - 42 9.4.6 error flag (error) the error is signalled on the errn pin according to table 6 and table 8 . the flag is set if at least one of the error flags in chapters 9.4.2 to 9.4.5 is set. the flag will be reset if none of the flags in chapters 9.4.2 to 9.4.5 is set. 9.5 status flags 9.5.1 local wake flag (lwake) see chapter 8.7 wake-up events on page 16 9.5.2 remote wake flag (rwake) see chapter 8.7 wake-up events on page 16 9.5.3 power on flag (pwon) the pwon is set leaving the power-off state and it is reset entering a low-power mode after a non-low-power mode. 9.6 error flags and st atus flags read-out the readout mechanism consists of two information groups: 1. error read-out 2. status information read-out the read-out mechanism as serial transmission on pin en and errn: the error flags and the status flags can be read-out by applying a clock signal to pin en in a non-low-power mode. a falling ed ge on pin en starts the read-out loading the content of the error/status flag into the shift register and signaling the error flag on the errn pin. on the second falling edge the first flag (bit 0) will be shifted out. the errn data is valid after t ro_en_errn . if en pin keeps on toggling after the last flag (bit 15) the next flag again is bit 0. the complete list of bits is shown in table 10 . if no transition is detected on pin en for longer than t ro_en_timeout the device enters the operation mode selected by the host pins. figure 10. timing of the read-out mechanism table 9. read-out mechanism and transceiver states state enabled / disabled normal mode enabled receive-only mode enabled standby mode disabled go-to-sleep mode disabled sleep mode disabled en errn 50% v io error flag bit 0 bit 1 bit 2 t < t ro_en_timeout t ro_en_errn t > t ro_en__timeout errn errn 50% v io
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 24 - 42 9.6.1 error and status flag bit order when the read-out mechanism is started, the first data information is the bit 0 until bit 15 is transmitted. any re-initiation or repetitions is started with the first data bit 0. 9.7 bus driver 9.7.1 bus states activity: the bus wires reflects the differential signal specified in chapter 9.9 transmitter on page 26 . idle: the bus wires are terminated to v cc /2 via. receiver input resistances. idle_lp: the bus wires are terminated to gnd via receiver input resistances. idle_hz: the bus wires are not terminated to v cc /2 via. 1m ? table 10. bit order for the read-out sequence bit description symbol bit 0 undervoltage v bat detected uvv bat _det bit 1 undervoltage v io detected uvv io _det bit 2 undervoltage v cc detected uvv cc _det bit 3 bus error buserr bit 4 reserved reserved bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 short circuit between bp and bm bp_bm bit 11 over temperature ot bit 12 txen_bge timeout txen_to bit 13 local wake flag lwake bit 14 remote wake flag rwake bit 15 power on flag pwon
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 25 - 42 9.8 transceiver timing figure 11. timing diagram 80 % 20 % txd bge txen v bus rxd rxen 0.5 * v io 300 mv 30 mv t txen_bus_active_idle t txen_bus_idle_active t bge_bus_active_idle t bge_bus_idle_active t txd_bus01 t txd_bus10 t bus_rxd01 t bus_rxd10 t busidlereaction t busactivityreaction t bus01 t bus10 30 mv -300 mv -300 mv -300 mv t bus_idle_active t bus_active_idle 0.5 * v io 0.5 * v io 0.5 * v io 0.5 * v io
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 26 - 42 9.9 transmitter the transmitter generates out of a digital input signal on txd the flexray differential bus voltage. the transmitter is only ac tive in normal mode if bge is on logical high and txen is on logical low. figure 12. transmitter characteristics (txd ? bus) figure 13. transmitter characteristics (txen ? bus) v txd v bus -v bus_diff_idle + v bus_diff_idle v bus_diff_d1 v bus_diff_d0 t txd_bus01 t txd_bus10 t bus01 t bus10 data1: x * t bit data0: x * t bit data1: x * t bit data0: x * t bit 50% * v io 80% * v bus_diff_d1 300 mv -300 mv 20% * v bus_diff_d1 v txen v bus -v bus_diff_idle + v bus_diff_idle v bus_diff_d1 v bus_diff_d0 t txen_bus_active_idle t bus_idle_active t bus_active_idle 300 mv - 300 mv 50% * v io t txen_bus_idle_active < t txen_timeout < t txen_timeout
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 27 - 42 figure 14. timing characteristics (bge ? bus) in normal and receive-only mode, the transmitter drives on the bu s idle in case no data are transmitted. in standby, go-to-slee p and sleep mode the transmitter dr ives idle_lp on th e bus pins. in power-off mode the bus pins shows idle_hz. 9.10 receiver the receiver generates from the flexray differential bus voltage a digital signal on the rxd and rxen pins. rxd shows the data (data0 and data1) and rxen shows the bus idle and activity status received on the bus pins. the receiver is only active in normal and rece ive-only mode. figure 15. timing characteristics of the bus signals to rxd and rxen v bge v bus -v bus_diff_idle + v bus_diff_idle v bus_diff_d1 v bus_diff_d0 t bge_bus_active_idle t bus_idle_active t bus_active_idle 300 mv -300 mv 50% * v io t bge_bus_idle_active v bus -v bus_diff_idle + v bus_diff_idle t rxd_fall v busactivehigh v data1 v busactivelow v data0 v rxen 50% * v io v rxd 20% * v io 80% * v io t busactivityreaction t bus_rxd10 t bus_rxd01 t rxd_rise t busidlereaction data0: x * t bit data1: x * t bit 50% * v io 300 mv -300 mv
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 28 - 42 9.10.1 bus activity and idle detection ( only in normal and receive-only mode) if the absolute differential bus voltage is higher than v busactivelow and less than v busactivehigh for a time longer than t busidledetection , bus idle is detected, rxen and rxd are switched to logical high after a time t busidlereaction . if the absolute differential bus voltage is higher than v busactivehigh or lower than v busactivelow for a time loner than t busactivitiydetection , bus activity is detected, rxen is switched to logical low and rxd shows the detected bus data according to table 11 after the time t busactivityreaction . 9.10.2 bus data detection (only in normal and receive-only mode) if, after activity detection the differential bus voltage is higher than v data1 , rxd will be high after a time t bus_rxd01 . if, after activity detection the differential bus voltage is lower than v data0 , rxd will be low after a time t bus_rxd10 . figure 16. receiver characteristics (bus ? rxd, rxen) table 11. logic table for receiver bus signal detection receiver operation mode bus signals rxen rxd normal power modes (normal and receive-only mode) idle h h data0 l l data1 l h v rxd v bus v busactivelow v data0 v busactivehigh v data1 data0 activity idle data1 activity v rxen v bus v bus v bus
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 29 - 42 9.10.3 receiver test signal figure 17. receiver test signal 22 ns 22 ns t bit t bus_rxd01 t bus_rxd10 v bus rxd 300mv -300mv 400mv -400mv t bus_rxd10 t bus_rxd01 t bit v bus rxd 22 ns 22 ns 300mv -300mv 400mv -400mv
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 30 - 42 9.11 test circuits figure 18. test circuit for automotive transients figure 19. test circuit for dynamic characteristics as8221 rxd bp bm rl cl 15pf vbat vcc vio 100nf +5v 10uf 14 19 4 7 18 17 1nf 1nf iso 7637 pulse generator iso 7637 pulse generator 12v or 42v transients in accordance with iso7637: test pulses 1, 2, 3a, 3b, 4, 5 test conditions: normal mode bus idle, normal mode bus active (txd=5 mhz, txen=1khz) as8221 rxd bp bm rl cl 15pf vbat vcc vio 100nf +5v +12v 10uf 14 19 4 7 18 17
as8221 datasheet - application information www.austriamicrosystems.com/flexray/as8221 revision 1.7 31 - 42 9.12 application circuits figure 20. as8221 application schematic
as8221 datasheet - appendix www.austriamicrosystems.com/flexray/as8221 revision 1.7 32 - 42 10 appendix 10.1 flexray functional classes the as8221 flexray standard transceiver has the following bus driver functional classes according the flexray electrical physic al layer specification v2.1 rev. b implemented: ?? functional class: chapter 8.13.1 ?bus driver voltage regulator control? ?? functional class: chapter 8.13.2 ?bus driver - bus guardian interface? ?? functional class: chapter 8.13.4 ?bus driver logic level adaptation? 10.2 flexray parameter comparison the following table shows the comparison of conventions used in as8221 datasheet and flexray electrical physical layer specific ation v2.1 rev. b. table 12. comparison table as8221 datasheet flexray electrical physical layer specification v2.1 rev. b symbol parameter name description absolute maximum ratings - battery supply voltage (v bat )- - - supply voltage (v cc )- - - supply voltage (v io )- - - dc voltage at en, stbn, errn, txd, rxd, txen, bge, rxen -- - dc voltage on pin wake, inh1, inh2 - - - dc voltage at bp and bm - - - input current (latchup immunity) - - - electrostatic discharge at bus lines bp, bm, v bat , wake uesdext esd protection on pins that lead to ecu external terminals - electrostatic discharge uesdint esd on all other pins - transient voltage on bp, bm - - - transient voltage on v bat -- - total power dissipation (all supplies and outputs) -- - storage temperature - - - junction temperature - - - package body temperature - - - humidity non-condensing - - supply voltage t amb ambient temperature t ambient temperature v cc - v io difference of supplies - - i bat v bat current consumption -- i cc v cc current consumption --
as8221 datasheet - appendix www.austriamicrosystems.com/flexray/as8221 revision 1.7 33 - 42 i io v io current consumption -- state transitions t stbn_rxd delay stbn high to rxd high with wake flag set -- t stbn_rxen delay stbn high to rxen high with wake flag set -- t sleep_inh1 delay stbn high to inh1 high - - t standby_inh2 delay stbn high to inh2 high - - t sleep go-to-sleep hold time - - transmitter v bus_diff_d0 differential bus voltage low in normal mode (data0) ubdtx active absolute value of ubus while sending v bus_diff_d1 differential bus voltage high in normal mode (data1) ubdtx active absolute value of ubus while sending v bus_diff matching between data0 and data1 differential bus voltage in normal mode -- v bus_com_d0 common mode bus voltage in case of data0 in non-low-power modes -- v bus_com_d1 common mode bus voltage in case of data1 in non-low-power modes -- ? v bus_com matching between data0 and data1 common mode voltage -- v bus_diff_idle absolute differential bus voltage in idle mode ubdtxidle absolute value of ubus, while idle ibp bmshortmax ibm bpshortmax absolute maximum current when bp is shorted to bm ibp bmshortmax ibm bpshortmax absolute maximum output current when bp shorted to bm ibp gndshortmax absolute maximum current when bp is shorted to gnd ibp gndshortmax absolute maximum output current when shorted to gnd ibm gndshortmax absolute maximum current when bm is shorted to gnd ibm gndshortmax absolute maximum output current when shorted to gnd ibp -5vshortmax absolute maximum current when bp is shorted to -5v ibp -5vshortmax absolute maximum output current when shorted to -5v ibm -5vshortmax absolute maximum current when bm is shorted to -5v ibm -5vshortmax absolute maximum output current when shorted to -5v ibp 27vshortmax absolute maximum current when bp is shorted to 27v ibp bat27vshortmax absolute maximum output current when shorted to 27v ibm 27vshortmax absolute maximum current when bm is shorted to 27v ibm bat27vshortmax absolute maximum output current when shorted to 27v table 12. comparison table as8221 datasheet flexray electrical physical layer specification v2.1 rev. b symbol parameter name description
as8221 datasheet - appendix www.austriamicrosystems.com/flexray/as8221 revision 1.7 34 - 42 ibp 48vshortmax absolute maximum current when bp is shorted to 48v ibp bat48vshortmax absolute maximum output current when shorted to 48v ibm 48vshortmax absolute maximum current when bm is shorted to 48v ibm bat48vshortmax absolute maximum output current when shorted to 48v t txd_bus01 delay time from txd to bus positive edge dbdtx10 transmitter delay, negative edge t txd_bus10 delay time from txd to bus negative edge dbdtx01 transmitter delay, positive edge t txd_mismatch delay time from txd to bus mismatch dtxasym transmitter delay mismatch | dbdtx10 - dbdtx01 | t bus10 fall time differential bus voltage dbustx10 fall time differential bus voltage (80% ? 20%) t bus01 rise time differential bus voltage dbustx01 rise time differential bus voltage (20% ? 80%) t txen_bus_idle_active delay time from txen to bus active dbdtxia propagation delay idle ?active t txen_bus_active_idle delay time from txen to bus idle dbdtxai propagation delay active ? idle t txen_mismatch delay time from txen to bus mismatch dbdtxdm | dbdtxia - dbdtxai | t bge_bus_idle_active delay time from bge to bus active dbdtxia propagation delay idle ? active t bge_bus_active_idle delay time from bge to bus idle dbdtxai propagation delay active ? idle t bus_idle_active differential bus voltage transition time: idle to active dbustxia transition time idle ? active t bus_active_idle differential bus voltage transition time: active to idle dbustxai transition time active ? idle t txen_timeout txen timeout - - receiver r bp , r bm bp, bm input resistance rcm1, rcm2 receiver common mode input resistance r diff bp, bm differential input resistance - - v bpidle , v bmidle idle voltage in non-low-power modes on pin bp,bm ubias bus bias voltage during bd_normal mode v bpidle_low , v bmidle_low idle voltage in low-power modes on pin bp, bm ubias bus bias voltage during low-power modes i bpidle absolute idle output current on pin bp - - i bmidle absolute idle output current on pin bm - - i bpleak , i bmleak absolute leakage current, when not powered ibpleak, ibmleak absolute leakage current, when not powered table 12. comparison table as8221 datasheet flexray electrical physical layer specification v2.1 rev. b symbol parameter name description
as8221 datasheet - appendix www.austriamicrosystems.com/flexray/as8221 revision 1.7 35 - 42 v busactivehigh activity detection differential input voltage high ubusactivehigh upper receiver threshold for detecting activity v busactivelow activity detection differential input voltage low ubusactivelow lower receiver threshold for detecting activity v data1 data1 detection differential input voltage udata1 receiver threshold for detecting data_1 v data0 data0 detection differential input voltage udata0 receiver threshold for detecting data_0 v dataerr mismatch between data0 and data1 differential input voltage udata mismatch of receiver thresholds v receive_com maximum common mode voltage range when receiving ucm common mode voltage range (with respect to gnd) that does not disturb the receive function t bus_rxd10 delay from bus to rxd negative edge dbdrx10 receiver delay, negative edge t bus_rxd01 delay from bus to rxd positive edge dbdrx01 receiver delay, positive edge t bit bit time - - t rxd_asym delay time from bus to rxd mismatch drxasym receiver delay mismatch | dbdrx10 ? dbdrx01 | t rxd_fall fall time rxd voltage drxslope fall and rise time 20%-80% t rxd_rise rise time rxd voltage drxslope fall and rise time 20%-80% t busidledetection idle detection time didledetection filter-time for idle detection t busactivitydetection activity detection time dactivitydetection filter-time for activity detection t busidlereaction idle reaction time dbdrxai idle reaction time t busactivityreaction activity reaction time dbdrxia activity reaction time wake-up detector t bwu_d0 data0 detection time in remote wake-up pattern dwu0detect acceptance timeout for detection of a data_0 phase in wake-up pattern t bwu_idle idle or data1 detection time in remote wake- up pattern dwuidledetect acceptance timeout for detection of a idle phase in wake-up pattern t bwu_detect total remote wake-up detection time dwutimeout acceptance timeout for wake-up pattern recognition v bwuth bus wake-up detection threshold - - v lwuth local wake-up detection threshold - - table 12. comparison table as8221 datasheet flexray electrical physical layer specification v2.1 rev. b symbol parameter name description
as8221 datasheet - appendix www.austriamicrosystems.com/flexray/as8221 revision 1.7 36 - 42 i lwul low level input current on local wake pin - - i lwuh high level input curren t on local wake pin - - t lwufilter local wake filter time dwakepulsefilter wake pulse filter time (spike rejection) - v bat operating range v bat = +6.5 to + 50v v bat for wu detector battery voltage required for wake-up detector operation supply voltage monitor v batthh v bat undervoltage recovery threshold -- v batthl v bat undervoltage detection threshold uuvbat undervoltage detection threshold v ccthh v cc undervoltage recovery threshold -- v ccthl v cc undervoltage detection threshold uuvcc undervoltage detection threshold v iothh v io undervoltage recovery threshold -- v iothl v io undervoltage detection threshold uuvio undervoltage detection threshold t uv_detect detection time for undervoltage at v bat , v cc , v io duvbat, duvcc, duvio undervoltage reaction time t uv_rec detection time for undervoltage recovery at v bat , v cc , v io -- bus error detection i thl absolute bus current for low current detection - - i thh absolute bus current for high current detection - - v short differential voltage on bp and bm for detecting short circuit between bus lines -- t bus_error bus error detection time - detection only required while actively transmitting a data frame, error indication to host latest when transmission stops. over temperature ot th over temperature threshold - - ot tl over temperature hysteresis - - table 12. comparison table as8221 datasheet flexray electrical physical layer specification v2.1 rev. b symbol parameter name description
as8221 datasheet - appendix www.austriamicrosystems.com/flexray/as8221 revision 1.7 37 - 42 power supply interface v oinh high level voltage drop on inh1, inh2 - - | i il | leakage current - - communication controller interface v txdih threshold for detecting txd as on logical high uvio-in-high threshold for detecting a digital input as on logical high v txdil threshold for detecting txd as on logical low uvio-in-low threshold for detecting a digital input as on logical low i txdih txd high level input current - - i txdil txd low level input current - - v txenih threshold for detecting txen as on logical high uvio-in-high threshold for detecting a digital input as on logical high v txenil threshold for detecting txen as on logical low uvio-in-low threshold for detecting a digital input as on logical low i txenih txen high level input current - - i txenil txen low level input current - - v rxdoh rxd high level output voltage uvio-out-high output voltage on a digital output, when in logical high state v rxdol rxd low level output voltage uvio-out-low output voltage on a digital output, when in logical low state host interface v stbnih threshold for detecting stbn as on logical high uvio-in-high threshold for detecting a digital input as on logical high v stbnil threshold for detecting stbn as on logical low uvio-in-low threshold for detecting a digital input as on logical low i stbnih stbn high level input current - - i stbnil stbn low level input current - - t stbn_deb_lp stbn de-bouncing time low-power modes - - t stbn_deb_nlp stbn de-bouncing time non-low-power modes -- v enih threshold for detecting en as on logical high uvio-in-high threshold for detecting a digital input as on logical high table 12. comparison table as8221 datasheet flexray electrical physical layer specification v2.1 rev. b symbol parameter name description
as8221 datasheet - appendix www.austriamicrosystems.com/flexray/as8221 revision 1.7 38 - 42 v enil threshold for detecting en as on logical low uvio-in-low threshold for detecting a digital input as on logical low i enih en high level input current - - i enil en low level input current - - t en_deb_lp en de-bouncing time low-power modes - - t en_deb_nlp en de-bouncing time non-low-power modes - - v errnoh errn high level output voltage uvio-out-high output voltage on a digital output, when in logical high state v errnol errn low level output voltage uvio-out-low output voltage on a digital output, when in logical low state bus guardian interface v bgeih threshold for detecting bge as on logical high uvio-in-high threshold for detecting a digital input as on logical high v bgeil threshold for detecting bge as on logical low uvio-in-low threshold for detecting a digital input as on logical low i bgeih bge high level input current - - i bgeil bge low level input current - - v rxenoh rxen high level output voltage uvio-out-high output voltage on a digital output, when in logical high state v rxenol rxen low level output voltage uvio-out-low output voltage on a digital output, when in logical low state read out interface t ro_en_errn propagation delay falling edge en to errn - - t ro_en_timeout error-read-out timeout - - table 12. comparison table as8221 datasheet flexray electrical physical layer specification v2.1 rev. b symbol parameter name description
as8221 datasheet - package drawings and markings www.austriamicrosystems.com/flexray/as8221 revision 1.7 39 - 42 11 package drawin gs and markings the device is available in a ssop20 package. figure 21. package drawings and dimensions notes: 1. dimensions and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. marking information: yy ww i zz @ last two digits of the current year manufacturing week assembly plant identifier assembly traceability code sublot identifier symbol min nom max a- -2.00 a1 0.05 - - a2 1.65 1.75 1.85 b0.22-0.38 c0.09-0.25 d 6.90 7.20 7.50 e 7.40 7.80 8.20 e1 5.00 5.30 5.60 e - 0.65 bsc - l 0.55 0.75 0.95 l1 - 1.25 ref - l2 - 0.25 bsc - r0.09 - - ? 0o 4o 8o n20 as8221 @ yywwizz
as8221 datasheet - revision history www.austriamicrosystems.com/flexray/as8221 revision 1.7 40 - 42 revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.0 sep 01, 2009 hgl first version 1.1 sep 14, 2009 made sentence corrections and converted the ?typ? values of table 3 in to standard format. no technical changes to the datasheet. 1.2 may 13, 2010 updated the errn signalling table 8. (no functional change) updated ordering information table 13. added package drawings and markings ? refer to page 39. 1.3 july 16, 2010 updated ordering information table 13. 1.4 oct 30, 2010 updated the following: vbat minimum voltage requirement in electrical characteristics, error flags, error and status flag bit order. nov 18, 2010 updated absolute maximum ratings on page 6 , package drawings and markings on page 39 . dec 15, 2010 updated package body temperature under absolute maximum ratings. 1.5 feb 24, 2011 figure 12 , figure 13 , figure 14 , figure 15 , figure 16 updated. added application circuits. 1.6 dec 19, 2011 updated esd parameter in absolute maximum ratings on page 6 . 1.7 feb 16, 2012 updated package drawings and markings section.
as8221 datasheet - ordering information www.austriamicrosystems.com/flexray/as8221 revision 1.7 41 - 42 12 ordering information the devices are available as the standard products shown in table 13 . note: all products are rohs compliant and austriamicrosystems green. ? buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect ? ? technical support is available at http://www.austriamicrosystems.com/technical-support ? ? for further information and requests, please contact us mailto: sales@austriamicrosystems.com ? or find your local distributor at http://www.austriamicros ystems.com/distributor table 13. ordering information ordering code marking description delivery form package as8221-assp as8221 as8221 flexray standard transceiver tape & reel in drypack ssop20
as8221 datasheet - copyrights www.austriamicrosystems.com/flexray/as8221 revision 1.7 42 - 42 copyrights copyright ? 1997-2012, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. au striamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. ? contact information headquarters austriamicrosystems ag ? tobelbaderstrasse 30 ? a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 ? fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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